[sv-ac] variables vs. expressions

Hi,

I took an action item to review cases at SV, where there
are operations that are allowed on variables with a specific type,
but are not allowed on expressions with the same type.
Here they are:

1. sequence .matched, .trigger,  .ended

2. bit select and bit slice on vectors.

3. the methods first(), last(), next(),  prev(), num(), name() of enum 
types.
    There  is no explicit language saying that these methods should not be
     used on expression, but I think that one may conclude it from the text.

4. I read the aggregate data types clause and the cast clause, I cannot say
    whether the following code is legal:

    typedef struct {bit a; bit b;} AB;

    assert property((AB'(2'b10)).a ==1);

    Does anybody know?

Doron


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