RE: [sv-ac] variables vs. expressions

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Doron Bustan
Sent: Wednesday, May 30, 2007 5:46 PM
To: Korchemny, Dmitry; sv-ac@server.eda.org
Subject: [sv-ac] variables vs. expressions

4. I read the aggregate data types clause and the cast clause, I cannot
say
    whether the following code is legal:

    typedef struct {bit a; bit b;} AB;

    assert property((AB'(2'b10)).a ==1);

    Does anybody know?
[Yulik] No, it is not legal, for the same reason the bit/part selects
are not legal on "non-leaf" expressions:

primary ::=
[ implicit_class_handle . | class_scope | package_scope ]
hierarchical_identifier select

select ::=
[ { . member_identifier bit_select } . member_identifier ] bit_select [
[ part_select_range ] ]

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