FW: [sv-ac] if..else and 4-state conditions

From: Eduard Cerny <Eduard.Cerny_at_.....>
Date: Wed May 02 2007 - 05:37:56 PDT
Hi,

I suppose when assertions are to be synthesized, a different form,
simpler one, that does not respect 4-state semantics would be used.

ed 

-----Original Message-----
From: Brad Pierce 
Sent: Tuesday, May 01, 2007 6:14 PM
To: Eduard Cerny
Subject: RE: [sv-ac] if..else and 4-state conditions

I don't know, because neither of them is synthesizable.

-- Brad 

-----Original Message-----
From: Eduard Cerny [mailto:edcerny@synopsys.COM] 
Sent: Tuesday, May 01, 2007 2:14 PM
To: Brad Pierce
Subject: RE: [sv-ac] if..else and 4-state conditions

Is it simpler, I mean more efficient, than cast and negate? 
ed

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of 
> Brad Pierce
> Sent: Tuesday, May 01, 2007 4:40 PM
> To: sv-ac@eda-stds.org
> Subject: Re: [sv-ac] if..else and 4-state conditions
> 
> A simpler way to write that condition is
> 
>    1'b0 inside {b!=0}
> 
> -- Brad
> 
> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of 
> John Havlicek
> Sent: Tuesday, May 01, 2007 1:07 PM
> To: sv-ac@eda-stds.org
> Subject: [sv-ac] if..else and 4-state conditions
> 
> All:
> 
> We talked some in today's meeting about aligning enabling conditions 
> and property if..else to the Verilog if..else semantics for 4-state 
> conditions.
> 
> Similar considerations apply to case conditions.
> 
> Jonathan Bromley suggested
> 
>   !(bit'(b!=0))
> 
> to get a condition for the "else" of  "if(b) .. else ..".
> 
> I made a little table for this:
> 
>   b   b!=0  bit'(b!=0)  !(bit'(b!=0))
>   -----------------------------------
>   0     0        0            1
>   1     1        1            0
>   x     x        0            1
>   z     x        0            1
> 
> 
> Assuming I filled in the table correctly, it seems to work.
> 
> I think that the idiom "b!=0" takes care of variability in the 
> bitwidth of b, and Jonathan said that this idiom is more widely 
> applicable than, say, unary "or" reduction (i.e., "|b").
> 
> J.H.
> 
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Received on Wed May 2 05:38:20 2007

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