Apologies, I mistakenly sent this response to Brad Pierce instead of sv-ac at first. ~~~~~~~~~~~~~~~~~ > A simpler way to write that condition is > > 1'b0 inside {b!=0} Urrrm, what is the meaning of 1'b0 inside {1'bx} ? Actually, my original suggestion was (almost) (b!=0) !== 1'b1 // originally I forgot the 1'b size which seems to me to be simpler still; but I (willingly) conceded that !bit'(b!=0) was neater. Surely the point here is that we need two expressions that are guaranteed to be (a) 2-state, (b) complements; both bit'() , !bit'() and ===1'b1 , !==1'b1 fit the requirements in a rather obvious way. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed May 2 05:01:45 2007
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