Re: [sv-ac] if..else and 4-state conditions

A simpler way to write that condition is

   1'b0 inside {b!=0} 

-- Brad

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of John
Havlicek
Sent: Tuesday, May 01, 2007 1:07 PM
To: sv-ac@eda-stds.org
Subject: [sv-ac] if..else and 4-state conditions

All:

We talked some in today's meeting about aligning enabling conditions and
property if..else to the Verilog if..else semantics for 4-state
conditions.

Similar considerations apply to case conditions.

Jonathan Bromley suggested 

  !(bit'(b!=0))

to get a condition for the "else" of  "if(b) .. else ..".

I made a little table for this:

  b   b!=0  bit'(b!=0)  !(bit'(b!=0))
  -----------------------------------
  0     0        0            1
  1     1        1            0
  x     x        0            1
  z     x        0            1


Assuming I filled in the table correctly, it seems to work.

I think that the idiom "b!=0" takes care of variability in the bitwidth
of b, and Jonathan said that this idiom is more widely applicable than,
say, unary "or" reduction (i.e., "|b").

J.H.

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