[sv-ac] passing constant value in actual argument

Hi , 
     I have a quary regarding passing argument .

Please consider this case:

sequence seq(a, b, n);
!a ##1 a[*n] ##1 b[*n];
endsequence

property p1;
@(posedge clk)
(reset ##1 !reset)|=> seq(out[1], out[2], 2);
endproperty

assert property (p1);

Is it a valid case? my doubt is  in sequence expression of the sequnce 
'seq' 'n' should be constant, in this case 'n' is getting constant value 
from the actual argument in property expression, so this is valid 
case,am I correct? Please comment on my understanding from LRM.

Thanks
Soumya