RE: [sv-ac] passing constant value in actual argument

In my view it is a vlaid definition and instance. The actual parameters
are  substituted and then checked.

ed

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On 
> Behalf Of Soumya Jyoti Wadader
> Sent: Wednesday, November 01, 2006 7:06 AM
> To: sv-ac@eda.org
> Subject: [sv-ac] passing constant value in actual argument 
> 
> Hi , 
>      I have a quary regarding passing argument .
> 
> Please consider this case:
> 
> sequence seq(a, b, n);
> !a ##1 a[*n] ##1 b[*n];
> endsequence
> 
> property p1;
> @(posedge clk)
> (reset ##1 !reset)|=> seq(out[1], out[2], 2);
> endproperty
> 
> assert property (p1);
> 
> Is it a valid case? my doubt is  in sequence expression of 
> the sequnce 
> 'seq' 'n' should be constant, in this case 'n' is getting 
> constant value 
> from the actual argument in property expression, so this is valid 
> case,am I correct? Please comment on my understanding from LRM.
> 
> Thanks
> Soumya
>