Hi, I'd like to mention that in the last Champions meeting, the subject was brought up again about issues being or to be discussed in SV-AC which should be brought to the attention of SV-BC and/or SV-EC. This is because some of the issues are not or should not be limited just to assertions, or because they use existing constructs in a new and maybe different way, etc. etc. Examples are 1641 and 1646-1648. A future example which was specifically mentioned is the 'let' construct. Because the SV-AC members are less involved in the SV-BC and SV-EC committees and maybe have less experience and knowledge of the SystemVerilog language 'spirit', SV-AC members may not always be aware of the implications of their issues and in some cases the issues are at least jointly in the scope of other committees. So this is a call to try to be aware of such cases and to call the attention of the other committees to them. This will help prevent bad feelings between the committees. It is better to be a little too cautious in this matter rather than not careful enough. Thanks, Shalom > -----Original Message----- > From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On > Behalf Of Eduard Cerny > Sent: Tuesday, October 31, 2006 9:00 PM > To: sv-ac@server.eda.org > Subject: [sv-ac] IEEE 1800 SV-AC : minutes of meeting on 10/31/2006 > > Please let me know if corrections are required. > Best regards, > edReceived on Wed Nov 1 03:34:39 2006
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