Hi John, I have uploaded an updated proposal(severity_tasks_2.htm) which takes care of issues 1 and 2. This proposal also takes care of Shalom's comment about printing of simulation time. I do not quite understand your point 3. In what situations you think someone may call $error as a match item subroutine ? Also, how do we use it as part of evaluation. Could you please elaborate on this. Thanks. Manisha -----Original Message----- From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On Behalf Of John Havlicek Sent: Saturday, October 21, 2006 9:14 AM To: sv-ac@server.eda-stds.org Subject: Re: [sv-ac] new mantis item and proposal #1641 Hi Manisha: This is an excellent proposal. I had something similar on my list of enhancements and had not got around to posting a mantis item. I have a few comments. 1. For severity tasks in general sequential code, did you intend only to require line number, or did you really intend both file name and line number to be printed? 2. I think there is some more language in Section 17 that could benefit from some touch up to be consistent with the relaxation of the rule that the severity tasks be used only in the "else" action block. E.g., the paragraph beginning Because the assertion is a statement that something must be true ... on p. 232. Also, we might want to say a little more in 17.13 to make it clearer that the same conventions for using severity tasks in action blocks of immediate assertions apply to concurrent assertions. 3. Another topic is the use of severity tasks as subroutine calls attached to sequences. I think we should consider whether the result of the assertion evaluation should be sensitive to something like a $error called as a subroutine attached to a sequnce. Best regards, John H. > Hello, > =20 > I have filed a new mantis item #1641. A proposal has been added to > enable usage of assertion severity system tasks in general Verilog code. > =20 > Thanks. > ManishaReceived on Mon Oct 23 12:31:37 2006
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