Re: [sv-ac] new mantis item and proposal #1641

Hi Manisha:

This is an excellent proposal.  I had something similar on
my list of enhancements and had not got around to posting a
mantis item.

I have a few comments.

1. For severity tasks in general sequential code, did you 
   intend only to require line number, or did you really intend
   both file name and line number to be printed?

2. I think there is some more language in Section 17 that could
   benefit from some touch up to be consistent with the relaxation
   of the rule that the severity tasks be used only in the "else" 
   action block.  E.g., the paragraph beginning

      Because the assertion is a statement that something must
      be true ...

   on p. 232.  Also, we might want to say a little more in 17.13
   to make it clearer that the same conventions for using severity
   tasks in action blocks of immediate assertions apply to concurrent
   assertions.

3. Another topic is the use of severity tasks as subroutine calls
   attached to sequences.  I think we should consider whether 
   the result of the assertion evaluation should be sensitive to 
   something like a $error called as a subroutine attached to 
   a sequnce.

Best regards,

John H.

> Hello,
> =20
> I have filed a new mantis item #1641. A proposal has been added to
> enable usage of assertion severity system tasks in general Verilog code.
> =20
> Thanks.
> Manisha