Re: [sv-ac] Tool support for assumptions?

Adam,
 <is there any common way to write SVA as comments >
  It can be done a la PSL with pragmas such as "sva". This would then 
allow sva code to be
  written for VHDL as well as verilog. The SV tool can then either 
integrate the pragmas, or better yet create an SV module with a bind to 
the HDL design.

  
--------------------------------------------------------------------------
 Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
 http://www.vhdlcohen.com/ ben_ f rom _abv-sva.org
 * Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
  * Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd 
Edition, 2004, ISBN 0-9705394-6-0
  * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 
0-9705394-2-8
 * Component Design by Example ", 2001 isbn 0-9705394-0-1
  * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 
0-7923-8474-1
  * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 
0-7923-8115
  
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 -----Original Message-----
 From: Adam Krolnik <krolnik@lsil.com>
 To: sv-ac@eda.org
 Sent: Tue, 08 Mar 2005 15:13:08 -0600
 Subject: [sv-ac] Tool support for assumptions?

 Hello All;

  I'm trying to understand what kind of support is there for assume 
statements.

 E.g.

 assume property (@(posedge clk) !a |-> !b);

 or

 property nothing;
 @(posedge clk)
 !a |-> !b;
 endproperty
 assume property (nothing);

 Are any tools going to be parsing and/or using these statements?

  Lastly, is there any common way to write SVA as comments or will I 
need to define a preprocessor definition for tools that will accept the 
SV assertion code?

 -- Adam Krolnik
 ZSP Verification Mgr.
 LSI Logic Corp.
 Plano TX. 75074
 Co-author "Assertion-Based Design"