Re: [sv-ac] Tool support for assumptions?

From: Clifford E. Cummings <cliffc_at_.....>
Date: Tue Mar 08 2005 - 13:27:11 PST
Hi, Adam -

I can't answer the assume question but I have thoughts on the SVA comments, 
etc. (Just my opinions so far).

At 01:13 PM 3/8/2005, Adam Krolnik wrote:

>Hello All;
>...
>Lastly, is there any common way to write SVA as comments or will I need to 
>define a preprocessor definition for tools that will accept the SV 
>assertion code?

This is an interesting topic from the SVA keyword -vs- PSL comment-based 
perspective.

Comment based offers the advantage that they can be inserted into the code 
and ignored by non-PSL tools. SVA assertions use keywords that can cause 
non-supportive-tool issues.

On the other hand, the keyword based permit `ifdef conditional compilation 
of certain properties and assertions to include or exclude certain 
individual or groups of assertions whereas comment-based cannot be 
controlled with conditional compilation.

The SVA action blocks also sure help with functional coverage testing.

Per your book (great book, by the way!) you are a big proponent of 
inserting assertions into the RTL code for review and clarity purposes (and 
I agree), but we may find that early-adopter engineers need to use SVA in a 
separate file and bind the file to the design to avoid the non-support issues.

We also find the verification engineers that are not allowed to touch old, 
golden RTL models, and therefore will bind the assertions to those designs.

Interesting topic.

Regards - Cliff

>--
>     Adam Krolnik
>     ZSP Verification Mgr.
>     LSI Logic Corp.
>     Plano TX. 75074
>     Co-author "Assertion-Based Design"

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training
Received on Tue Mar 8 13:30:57 2005

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