[sv-ac] Tool support for assumptions?

Hello All;

I'm trying to understand what kind of support is there for assume statements.

E.g.

assume property (@(posedge clk) !a |-> !b);

or

property nothing;
   @(posedge clk)
   !a |-> !b;
endproperty
assume property (nothing);


Are any tools going to be parsing and/or using these statements?

Lastly, is there any common way to write SVA as comments or will I need to define a 
preprocessor definition for tools that will accept the SV assertion code?


-- 
     Adam Krolnik
     ZSP Verification Mgr.
     LSI Logic Corp.
     Plano TX. 75074
     Co-author "Assertion-Based Design"