Re: [sv-ac] AC 196:

Hi Hillel;

You wrote:

>Justification of both capabilities is based on the fact that most popular languages
>support both
>types of parameters. This includes SystemVerilog.

What I was thinking for justification a set of properties/sequences is provided
that you wish to write and why the pass-by-value functionality should be included.

You wrote:

>For pass by value, this:
> reg val1, val2;
> ... (val1 = parameter_a, val2 = parameter_b, property_rule6(val1, val2)) ...
>becomes, this:
> ... property_rule6(parameter_a, parameter_b) ...
>which is already simpler. It also may execute faster.

However, IMHO, the most common cases of properties and sequences would be:

     property my_simple_property_with_arguments(valid, datum) ...

This would have an error prone declaration if one chooses to formally declare
the types of the arguments (hoping to provide a safety and documentation to the
user.)

    property my_simple_property_with_arguments(
        ref reg valid, // must be ref...
        ref reg datum // must be ref...
        );
   ...

Should the user forget to add the 'ref' keyword, they obtain a most likely invalid
property.

    property my_simple_property_with_arguments(
        reg valid, // Whoops! only one value now!
        reg datum // Whoops! only one value now!
        );
      ...

There has not been confusion on the model of sequences and properties being module like
or task call like before. I fear choosing a task call like model provides a more
dangerous syntax and little overall benefit. This model we speak of does not even impact
the implementation of sequences and properties. Thus I would ask that consideration be
given to ease of use, when choosing a conceptual model to explain a specification from.

     Thanks.

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074
    Co-author "Assertion-Based Design"
Received on Wed Nov 17 11:51:39 2004