RE: [sv-ac] AC 196:

Hillel,
the subsequenet email exchanges with others clarified what you meant. I will
see then th text in the proposal.
Best regards,
ed
 

> -----Original Message-----
> From: Miller Hillel-R53776 [mailto:r53776@freescale.com]
> Sent: Wednesday, November 17, 2004 12:36 PM
> To: Eduard.Cerny@synopsys.COM; 'Adam Krolnik'
> Cc: sv-ac@eda.org
> Subject: RE: [sv-ac] AC 196:
>
> Ed,
> What is not clear?
> Thanks
> Hillel
>
> -----Original Message-----
> From: Eduard Cerny [mailto:Eduard.Cerny@synopsys.com]
> Sent: Wednesday, November 17, 2004 7:21 PM
> To: Miller Hillel-R53776; Eduard.Cerny@synopsys.com; 'Adam Krolnik'
> Cc: sv-ac@eda.org
> Subject: RE: [sv-ac] AC 196:
>
>
> Hi Hillel,
>
> I understood what John meant but was not clear on what you
> want in the proposal.
>
> Regards,
> ed
>
>
> > -----Original Message-----
> > From: Miller Hillel-R53776 [mailto:r53776@freescale.com]
> > Sent: Wednesday, November 17, 2004 12:05 PM
> > To: Eduard.Cerny@synopsys.COM; 'Adam Krolnik'
> > Cc: sv-ac@eda.org
> > Subject: RE: [sv-ac] AC 196:
> >
> > Ed,
> >
> > Do you still need additional clarafication on what
> property/sequence
> > activation means, in addition to what John explained?
> >
> > Basically property activation is the same as property
> instantiation.
> > Property instantiation is not a good word because instantiation is
> > something you do statically in the context of Verilog while
> activation
> > is something you do dynamically.
> > In SystemVerilog I see properties/sequences activated dynamically.
> >
> > Thanks
> > Hillel
> >
> > I think it is important to explain a little more what "activated"
> > means. You are talking about activation of property instances,
> > not property declarations.
> >
> > If I write
> >
> > assert property (@(posedge clk) foo(a,b,c))
> >
> > then the instance foo(a,b,c) gets activated at each posedge of clk.
> > If I write
> >
> > assert property (@(posedge clk) seqA |-> goo(a,b,c))
> >
> > then, assuming that seqA is singly clocked, the instance
> > goo(a,b,c) gets activated at each posedge of clk that is an
> endpoint
> > of seqA.
> >
> > -----Original Message-----
> > From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]On Behalf Of
> > Eduard Cerny
> > Sent: Wednesday, November 17, 2004 4:47 PM
> > To: Miller Hillel-R53776; Eduard.Cerny@synopsys.com; 'Adam Krolnik'
> > Cc: sv-ac@eda.org
> > Subject: RE: [sv-ac] AC 196:
> >
> >
> > Hillel,
> >
> > What I meant is that John asked for clarification or more precise
> > specification about when the activation takes place.
> >
> > Bestest..
> > ed
> >
> >
> > > -----Original Message-----
> > > From: Miller Hillel-R53776 [mailto:r53776@freescale.com]
> > > Sent: Wednesday, November 17, 2004 8:29 AM
> > > To: 'Eduard.Cerny@synopsys.com'; 'Adam Krolnik'
> > > Cc: sv-ac@eda.org
> > > Subject: RE: [sv-ac] AC 196:
> > >
> > > Ed,
> > >
> > > Where did john mention this, I never found it? What do
> you mean by
> > > preponed region?
> > > I am not sure I follow your question.
> > >
> > > Sampling becomes optional and is not required before
> activating the
> > > sequence when passing by value.
> > >
> > > Regards
> > > Hillel
> > >
> > > -----Original Message-----
> > > From: Eduard Cerny [mailto:Eduard.Cerny@synopsys.com]
> > > Sent: Wednesday, November 17, 2004 3:16 PM
> > > To: Miller Hillel-R53776; 'Adam Krolnik'
> > > Cc: Eduard.Cerny@synopsys.com; sv-ac@eda.org
> > > Subject: RE: [sv-ac] AC 196:
> > >
> > >
> > > Hi Hillel,
> > >
> > > If I understand it right, then effectively passing by value would
> > > remove the sampling in preponed region (is it what we
> > want?). But, as
> > > John also mentioned, I am not clear on when the values are
> > taken from
> > > the variable passed through that kind of argument.
> > >
> > > ed
> > >
> > >
> > > > -----Original Message-----
> > > > From: Miller Hillel-R53776 [mailto:r53776@freescale.com]
> > > > Sent: Wednesday, November 17, 2004 6:13 AM
> > > > To: 'Adam Krolnik'
> > > > Cc: Eduard.Cerny@synopsys.COM; sv-ac@eda.org; Miller
> Hillel-R53776
> > > > Subject: RE: [sv-ac] AC 196:
> > > >
> > > > Adam,
> > > >
> > > > Your examples are correct.
> > > >
> > > > I prefer the form of a task because you have a definition
> > > of 'pass by
> > > > value' and 'pass by reference'. I believe that both of
> these are
> > > > needed. With modules I just have pass by reference. The
> 'pass by
> > > > value' saves the need of sampling and then calling the sequence.
> > > >
> > > > Thanks
> > > > Hillel
> > > >
> > > > -----Original Message-----
> > > > From: Adam Krolnik [mailto:krolnik@lsil.com]
> > > > Sent: Tuesday, November 16, 2004 10:39 PM
> > > > To: Miller Hillel-R53776
> > > > Cc: Eduard.Cerny@synopsys.com; sv-ac@eda.org
> > > > Subject: Re: [sv-ac] AC 196:
> > > >
> > > >
> > > >
> > > >
> > > > Hi Hillel, Eduard;
> > > >
> > > > So as a comparative set of properties, these are the
> > > equivalent forms,
> > > > correct?
> > > >
> > > >
> > > > property rule6_with_no_type(x, y);
> > > > ##1 x |-> ##[2:10] y;
> > > > endproperty
> > > >
> > > > property rule6_with_type(ref bit x, ref bit y);
> > > > ##1 x |-> ##[2:10] y;
> > > > endproperty
> > > >
> > > >
> > > > And these are definitely not the same...
> > > >
> > > > property rule6_with_no_type(x, y);
> > > > ##1 x |-> ##[2:10] y;
> > > > endproperty
> > > >
> > > > property rule6_wrong_type(bit x, bit y);
> > > > ##1 x |-> ##[2:10] y;
> > > > endproperty
> > > >
> > > >
> > > > I would have though the model was that of a module, not a
> > > model of a
> > > > task (call or
> > > > invocation.) With a model of a module, then ports would not
> > > need the
> > > > 'ref' keyword to be able to monitor the (possibly) changing
> > > (in time)
> > > > value of expressions.
> > > >
> > > >
> > > > Thanks.
> > > >
> > > > Adam Krolnik
> > > > Verification Mgr.
> > > > LSI Logic Corp.
> > > > Plano TX. 75074
> > > > Co-author "Assertion-Based Design"
> > > >
> > >
> >
>
Received on Wed Nov 17 09:44:37 2004