RE: [sv-ac] AC 196:

Adam,

Personly I would prefer not to add the ref prefix, however this is the approach taken by System Verilog when
activating tasks. I think lots of confusion will be avoided if we are consistent with the over all language.
In addition the syntax definition already exists. Taking on the syntax of modules is problematic because
properties/sequences can be activated dynamically, while module are activated statically.

Justification of both capabilities is based on the fact that most popular languages support both
types of parameters. This includes SystemVerilog.

For pass by value, this:

  reg val1, val2;

      ... (val1 = parameter_a, val2 = parameter_b, property_rule6(val1, val2)) ...

becomes, this:

     ... property_rule6(parameter_a, parameter_b) ...

which is already simpler. It also may execute faster.

Regards
Hillel

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]On Behalf Of Adam Krolnik
Sent: Wednesday, November 17, 2004 6:10 PM
To: Miller Hillel-R53776
Cc: sv-ac@eda.org
Subject: Re: [sv-ac] AC 196:

HI Hillel;

>Your examples are correct.
(Re-showing the examples)

SV-AC - these are equivalent in this proposal ... not the other way around !!

property rule6_with_no_type(x, y);
    ##1 x |-> ##[2:10] y;
endproperty

property rule6_with_type(ref bit x, ref bit y);
    ##1 x |-> ##[2:10] y;
endproperty

>I prefer the form of a task because you have a definition of 'pass by value' and 'pass
>by reference'. I believe that both of these are needed.

It would be good to provide justification, with examples, why both forms are necessary.
I believe that through the use of local variables one could obtain
the effect of pass by value only. E.g.

     reg val1, val2;

      ... (val1 = parameter_a, val2 = parameter_b, property_rule6(val1, val2)) ...

By capturing a value in a local parameter, we call the property and give it the
stored values.

I see users being confused and asking why 'ref' must be specified for all parameters.
Consider the user error of forgetting 'ref' and the user's confusion with his assertion
failing to detect errors because it only has the values from one point in time. This
feature is definitely at the level of *gotcha*, though it may be more powerful for
expert users in other ways. We need to take care that assertions don't become too
complex to easily use.

As a counter idea, I believe that through the use of local variables one could obtain
the effect of pass by value only. E.g.

If the pass by value capability remains, it will be necessary to explain that the
sequence/property model is that of a task call, not a module instantiation. Note that
the original proposed model by Synopsys was to inline assertions - a replacement of the
formal arguments with the actual arguments passed. There was no though of pass by value
or reference.

Lastly, this change of intellectual model does not match the existing models of OVA, OVL
and proprietary tools present in many leading organizations.

     Thanks.

     Adam Krolnik
     Verification Mgr.
     LSI Logic Corp.
     Plano TX. 75074
     Co-author "Assertion-Based Design"
Received on Wed Nov 17 08:54:42 2004