Re: [sv-ac] Alternative proposal for NBA assignment
Subject: Re: [sv-ac] Alternative proposal for NBA assignment
From: Surrendra Dudani (Surrendra.Dudani@synopsys.com)
Date: Fri Nov 14 2003 - 12:23:10 PST
Hi Adam,
Please see comments.
Surrendra
At 01:15 PM 11/14/2003 -0600, you wrote:
HI Surrendra;
I wrote:
This above sentence and restated as the third bullet in the next
paragraph means
that the method "triggered" only works for the reactive
region.
And if this is true, the example in your paper does not work as a module
statement:
forever
L3: @(posedge clk) sig3 <= sig4 && s.triggered;
This will never set sig3 to a 1'b1 - the expression (sig4 &&
s.triggered) is evaluated
in the active region, sig3 is assigned in the nonblocking region. The
primary,
s.triggered only has a nonzero value in the reactive region.
Yes, the example states that it is used in the program block
An example below illustrates the use of triggered in a program block,
using the prior definition of sequence s.
forever
L3: @ (posedge clk) sig3 <= sig4 && s.triggered;
In statement L3, s.triggered evaluates to true if there was a match of
sequence s in the current clock tick.
To allow one to write the above
verilog in a module I would like to see triggered
or ended to be a clock wide nonzero value - not an event, but a boolean
value.
.triggered is a boolean but it gets set after the evaluation of a
sequence, stays true during the rest of the simulation time unit, and
gets reset to false at the end of the time unit. (.triggered is a general
method that is allowed on declared events in SV3.1.)
This means that the correct value of .triggered can only be available in
post-observe region.
As the example in the proposal further suggests that to use this in a
module, you need to delay the execution by waiting on s_detect as below,
so that correct values of all signals are obtained.
An example below illustrates the use of triggered in a module, using
the prior definition of sequence s.
program p;
L4: assign
s_detect = !s_detect;
endprogram
always @ (posedge clk) begin
L5:
@(s_detect);
L6: sig5
<= sig6 && s.triggered;
end
Thus the question to sv-ac.
Should one write modeling code (satelite logic) in
program blocks? or should they be in interfaces/modules. Maybe this
should be
an sv-ec question as well.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
**********************************************
Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive, Suite 300
Marlboro, MA 01752
Tel: 508-263-8072
Fax: 508-263-8123
email: Surrendra.Dudani@synopsys.com
**********************************************
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