Subject: Re: [sv-ac] Alternative proposal for NBA assignment
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Nov 14 2003 - 11:15:50 PST
HI Surrendra;
I wrote:
This above sentence and restated as the third bullet in the next paragraph means
that the method "triggered" only works for the reactive region.
And if this is true, the example in your paper does not work as a module statement:
forever
L3: @(posedge clk) sig3 <= sig4 && s.triggered;
This will never set sig3 to a 1'b1 - the expression (sig4 && s.triggered) is evaluated
in the active region, sig3 is assigned in the nonblocking region. The primary,
s.triggered only has a nonzero value in the reactive region.
To allow one to write the above verilog in a module I would like to see triggered
or ended to be a clock wide nonzero value - not an event, but a boolean value.
Thus the question to sv-ac. Should one write modeling code (satelite logic) in
program blocks? or should they be in interfaces/modules. Maybe this should be
an sv-ec question as well.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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