[sv-ac] RE: [sv-ec] Today's meeting minutes (7 July 2003).

Subject: [sv-ac] RE: [sv-ec] Today's meeting minutes (7 July 2003).
From: David W. Smith (david.smith@synopsys.com)
Date: Tue Jul 08 2003 - 10:56:48 PDT

Hi Adam,

Is this a formal request from SV-AC (from the chair or co-chair) or a
request from you? Is this related to just assertions or to something more
general?

Regards
David

David W. Smith
Synopsys Scientist

Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124

Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email: david.smith@synopsys.com
http://www.synopsys.com

-----Original Message-----
From: Adam Krolnik [mailto:krolnik@lsil.com]
Sent: Tuesday, July 08, 2003 8:27 AM
To: David W. Smith; System Verilog Assertion
Subject: Re: [sv-ec] Today's meeting minutes (7 July 2003).

Hi David;

SV-AC has an enhancement for funtionality that was taken out of 3.1 due to
many issues. It is on our enhancement list and we would like SV-EC to
consider 'templates' (#2 on the list) for their Extensions list.

    THanks.

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074

-------- Original Message --------
Subject: [sv-ac] SV AC Enhancement List
Date: Mon, 28 Apr 2003 10:34:13 -0700
From: Stephen Meier <Stephen.Meier@synopsys.com>
To: System Verilog Assertion <sv-ac@eda.org>

Hi:

  From last meeting I have established list of running enhancements for
consideration in next language revision.

Please continue to send me ideas to add to the list so we have collective
memory.

Thanks,
Steve

Steve Meier (stephen.meier@synopsys.com) W: 650-584-4476, Cell: 408-393-8246

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