Subject: Re: [sv-ac] SVAC Meeting minutes 3/20/03
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Mar 21 2003 - 08:04:30 PST
Hi Steve, all;
We also talked briefly about support for enabled (gated) clocks.
The thought was that (clk & enable) would produce the desired effects and is supported
by the current methods.
However I do not believe that this is correct.
The question is are these two fragments equivalent.
always @(posedge (clk & enable)) q <= d;
vs.
always @(posedge clk) if (enable) q <= d; // q1 below
Running a small program to test this theory, here are the results from Vcs 6.0
I stripped out the negedge clk changes...
Compiler version 6.0; Runtime version 6.0; Mar 21 09:57 2003
q uses clk & enable.
q1 uses clk iff enable.
time clk d e q q1
10 1 1 1 0 x early
30 1 2 0 1 1 later
50 1 3 0 1 1
70 1 4 1 3 1 early
90 1 5 0 4 4 later
110 1 6 0 4 4
130 1 7 1 6 4 early
150 1 8 0 7 7 later
...
Notice that q and q1 are not the same. Q (clk & enable) changes when the enable is
asserted. Q1 (clk iff enable) changes 1 clock later. For Q, this is because when the
clock is asserted, the enable becomes the clocking event. However for Q1 the clocking
event is only based on clk and then Q1 is updated only if enable is asserted.
Thus I would recommend that the clocking proposal be updated to allow
@@(posedge clk iff enable)
as legal syntax. This syntax is already part of SystemVerilog.
Without this you will have a hole in multiple clock support. Clock gating/enable is
becoming a more and more common technique especially in power sensitive designs. Proper
support will be necessary to for ease of use with properties.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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