Subject: Re: [sv-ac] Meeting on Tuesday at 9:30 am PST
From: dudani@us04.synopsys.com
Date: Tue Feb 25 2003 - 08:39:17 PST
Hi Adam,
I will answer what I can.
Surrendra
At 05:00 PM 2/21/2003 -0600, you wrote:
>Good afternoon Faisal;
>
>
>Here are some issues I have with the remaining functionality discussed.
>
>
>11.10.2
>
> 1. Verilog does not allow declarations to be inside unnamed blocks.
> You can do this:
> ...
> begin : named
> reg a;
>
> But then reg 'a' is only visible within that named block.
>
Yes, this deviates from Verilog. In fact, embedding assertions also is
different due to context extraction.
>11.11
>
>1. There is no concrete definition of how templates are
>instantiated/expanded/etc.
> There have been mail discussions but no wording.
>
>2. There is no concrete definition of how parameters to templates work.
>
> A. Are they references? Thus needing a type.
> B. Are they substitutions? Thus not needing a type and anything is legal.
These are syntactic substitutions and do not require a type. In Version
0.80, there is optional type specification, which I believe should be removed.
Syntactic entities allowed as parameters to templates are:
- expressions (bit-vector expression, sequence, string)
- property, sequence, bool and function names
>3. Can I pass in a property/sequence to a template?
Yes.
>4. What does a variable declaration look like in a template? What is the
>initial value
> of any declared variable (how to I assign one?)
This is being defined as part of clock domain in SV-EC. We should track the
exact syntax agreed in that committee.
>5. What does a nonblocking assignment look like in a template. Surrendra
>provided an
> example of:
>
> assign areg <= a | b | c;
>
> The word 'assign' means two things in verilog, procedural continuous
> assign and
> continuous assign. Neither of these are nonblocking assignments.
>
> How do they work? how are they clocked? There is nothing written down
> about this.
same as 4. But these are clocked by the clock domain.
>6. How do you pass parameters by name to a template and obtain the default
>value?
> E.g.
>
> template hold(exp, min=0, max=15, clk);
> ...
>
> hold h1(
> .exp(s_exp),
> .min(), // use default value?
> .max(10),
> .clk // new SV connection.
> );
.min() will use the default value.
>7. Are tools required to generate a name for templates instantiated without
> an instance name? I.e. ' A tool shall generate a name...' or 'A tool
> may generate'
>
My suggestion would be "A tool shall generate a name...'"
>11.12
>
> 1. Only allowing one to bind a program block is too restrictive.
>
> Propose instead a more fundamental concept - extend.
>
> extend <module |instance>;
>
> <module stuff>
> endmodule
>
> This way you can add whatever you desire to add. Program blocks,
> templates,
> assertions, attributes, sattelite FSM code, etc.
I think this should be requested to some other committee, perhaps SV-EC.
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
>
>
>
**********************************************
Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive
Suite 300
Marlboro, MA 01752
Tel: 508-263-8072
Fax: 508-263-8123
email: dudani@synopsys.com
**********************************************
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