Subject: Re: [sv-ac] Meeting on Tuesday at 9:30 am PST
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Feb 21 2003 - 15:00:43 PST
Good afternoon Faisal;
Here are some issues I have with the remaining functionality discussed.
11.10.2
1. Verilog does not allow declarations to be inside unnamed blocks.
You can do this:
...
begin : named
reg a;
But then reg 'a' is only visible within that named block.
11.11
1. There is no concrete definition of how templates are instantiated/expanded/etc.
There have been mail discussions but no wording.
2. There is no concrete definition of how parameters to templates work.
A. Are they references? Thus needing a type.
B. Are they substitutions? Thus not needing a type and anything is legal.
3. Can I pass in a property/sequence to a template?
4. What does a variable declaration look like in a template? What is the initial value
of any declared variable (how to I assign one?)
5. What does a nonblocking assignment look like in a template. Surrendra provided an
example of:
assign areg <= a | b | c;
The word 'assign' means two things in verilog, procedural continuous assign and
continuous assign. Neither of these are nonblocking assignments.
How do they work? how are they clocked? There is nothing written down about this.
6. How do you pass parameters by name to a template and obtain the default value?
E.g.
template hold(exp, min=0, max=15, clk);
...
hold h1(
.exp(s_exp),
.min(), // use default value?
.max(10),
.clk // new SV connection.
);
7. Are tools required to generate a name for templates instantiated without
an instance name? I.e. ' A tool shall generate a name...' or 'A tool may generate'
11.12
1. Only allowing one to bind a program block is too restrictive.
Propose instead a more fundamental concept - extend.
extend <module |instance>;
<module stuff>
endmodule
This way you can add whatever you desire to add. Program blocks, templates,
assertions, attributes, sattelite FSM code, etc.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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