Subject: [sv-ac] Adding properties to modules using separate means.
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Feb 26 2003 - 10:27:02 PST
Hi Faisal;
I wrote:
Section 11.12 Binding properties to scopes or instances.
1. Only allowing one to bind a program block is too restrictive.
Propose instead a more fundamental concept - extend.
extend <module |instance>;
<module stuff>
endmodule
This way you can add whatever you desire to add. Program blocks, templates,
assertions, attributes, sattelite FSM code, etc.
Surrendra writes:
"I think this should be requested to some other committee, perhaps SV-EC."
I would like to propose that we request the SV-EC committee to solve the issue
being addressed by this section 11.12 (Binding properties to modules/instances.)
This is a larger issue that has implications of capabilities. Thus SV-EC is the
appropriate group to delegate a request for additional capabilities.
The SV-AC requests a new feature to allow a user to add property directives, property
declarations, sequence declations, templates, etc. (Whatever is necessary to support
inclusion of SV-AC defined elements) to existing modules/instances without requiring
these elements be colocated in the actual module itself.
Possibilities include:
1. bind <module|instance name> program_instantiation;
Effect is as if program instantiation was directly in module/instance.
Only verification elements (program blocks) are allowed.
2. extend <module|instance name>; <module item [, module_item]> endmodule
Effect is as if the additional module instances were directly in
the module.
Any components would be allowed unless restricted (e.g. port declarations.)
Comments? Thoughts?
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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