Subject: Re: [sv-ac] delay/concatenation syntax
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Feb 19 2003 - 17:00:39 PST
Hi Surrendra;
I'm confused.
We aren't supposed to bring up syntax proposals. Only the DWG is supposed to be doing
this...
The disadvantage you present for your proposal is too great!
>no default for concatenation with delay 1(;)
So every time I have to write a sequence, I will be writing ";[1] ".
I don't understand how this makes for less typing.
If both the sequence separator and the implication operator both were nonoverlapping
then you will have better consistency.
I will take a look at the vfv pdf you made. Thanks.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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