Subject: Re: [sv-ac] context extraction resend
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Feb 19 2003 - 16:35:36 PST
Hi Steve;
A few more questions:
>>o Page 4 - How does one specify a default clock?
>The default clock is specified in the clocking domain description coming
>from testbench in SV-EC. The current proposal for clocking domain
>defines a default clock for a module so if an assertion refers to signals
>within the module then the default clock is used as sampling condition.
What happens if I have multiple clocks in my design? Do I have to specify
a clocking domain for various regions?
What happens if I have multiple clocks in a module?
What happens if you have an assertion in a module that has no clock (it is
thus unclocked.) Is it a compilation error until you setup a default clock?
>> Function example using two references to function with assertion.
>This seems complicated. You could have default clocking coming
>implicitly which may not be immediately apparent. We may need to consider restricting
>assertions to not be defined inside of functions or tasks. Do you think we can
>make this type of restriction ? Another restriction is to say that
>any assertions inside of functions or tasks must be explicitly clocked.
No assertions in functions or tasks - hmmm. It would be nice - the example
I gave is quite reasonable. I believe Cindy has a similar example of an
assertion in a loop (where the loop index affects variables in the assertion.
>> declarations crossing block boundaries.
>Yes this is a departure from standard Verilog restrictions. We should review this
>further. There is value in getting the context extraction, but we should ensure it
>works robustly.
This is a big departure - changing scoping rules has the consequences of confusing
everyone. The problem is the declaration of properties, not the assignment of value.
Separating the declaration to a larger scope fixes this problem.
Making templates elements of hierarchy solves some problems.
Thanks Steve - see you tomorrow.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
This archive was generated by hypermail 2b28 : Wed Feb 19 2003 - 16:43:47 PST