Subject: RE: [sv-ac] Question about reference to data defined in sequence.
From: Bassam Tabbara (bassam@novas.com)
Date: Wed Feb 05 2003 - 16:01:11 PST
Yes Adam, I am. This becomes obvious, as you state, in the case of
sequences, semantically none of the other terms/concepts are precise
(rather have nasty undertones...). Substitution is cleaner in the sense
that there is no (remnant) "tie" between formal/actual. I.e. also
cleaner than "hierarchical ..." ...
"replace" is used in the section wording, that's ok too, as long as we
use it all over, and not alternate with other terms.
Thx.
-Bassam.
-- Dr. Bassam Tabbara Technical Manager, R&D Novas Software, Inc.http://www.novas.com (408) 467-7893
> -----Original Message----- > From: Adam Krolnik [mailto:krolnik@lsil.com] > Sent: Wednesday, February 05, 2003 3:36 PM > To: bassam@novas.com > Cc: john.havlicek@motorola.com; > Surrendra.Dudani@synopsys.com; sv-ac@eda.org > Subject: Re: [sv-ac] Question about reference to data defined > in sequence. > > > > > Hello Bassam; > > > Are you suggesting that the LRM describe it "the same" as substitution > - "more formally formal/actual substitution." ? > > I agree the other terms are not applicable, in particular > when sequences are involved. But for the other 'types' it is > equivalent to hierarchical references. > > > This is not like any of the current verilog language in the > LRM. We will have to improve the descriptions of templates > sufficiently to explain the uniqueness. > > > Thanks Bassam > > > Adam Krolnik > Verification Mgr > LSI Logic Corp. > Plano TX. 75074 >
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