Re: [sv-ac] Question about reference to data defined in sequence.

Subject: Re: [sv-ac] Question about reference to data defined in sequence.
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Feb 05 2003 - 15:35:39 PST

Hello Bassam;

Are you suggesting that the LRM describe it "the same" as substitution
  - "more formally formal/actual substitution." ?

I agree the other terms are not applicable, in particular when sequences are involved.
But for the other 'types' it is equivalent to hierarchical references.

This is not like any of the current verilog language in the LRM. We will have to improve
the descriptions of templates sufficiently to explain the uniqueness.

   Thanks Bassam

    Adam Krolnik
    Verification Mgr
    LSI Logic Corp.
    Plano TX. 75074

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