Re: [sv-ac] Question about reference to data defined in sequence.


Subject: Re: [sv-ac] Question about reference to data defined in sequence.
From: John Havlicek (john.havlicek@motorola.com)
Date: Wed Feb 05 2003 - 15:34:21 PST


Adam:

I think these are important questions. Hopefully the DWG members
can provide some answers about the intended capabilities for
parameters.

J.H.

> Hi John;
>
>
> Or how about this version which would allow the encapsulation I desire.
>
> The template has as an argument a sequence (check_seq) that will be called from
> within the template. When it is called, it passes in the dynamic data reference.
>
>
> // A user defined sequence...
> sequence check_data(data) = (data == fifo_out_data);
>
> // A standard template for use whereever.
> template tem(check_seq);
> ast: assert (fifo_push => ((int itsdata = fifo_in_data) [1:100] fifo_pop;
> [0] check_seq(itsdata)))
> else $error();
> endtemplate
>
> // Instantiate the template with the specific data checking sequence.
> tem my_tem(check_data);
>
>
> Or with more arguments:
>
> template tem(clk,
> fifo_push,
> fifo_in_data,
> fifo_pop,
> check_seq);
>
> ast: assert @(posedge clk)
> (fifo_push => ((int itsdata = fifo_in_data) [1:100] fifo_pop;
> [0] check_seq(itsdata)))
> else $error();
> endtemplate
>
>
> tem my_tem(clk, fifo_push, fifo_in_data, fifo_pop, check_seq);
>
> So what else could be parameterized?
> The maximum value in the range above? [1:100] - could it be [1:latency] ?
> The width of declared dynamic data? int itsdata - could it be [W-1:0] itsdata?
>
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
>
>



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