Re: [sv-ac] Re: R58c - access to past values ... with enable

Subject: Re: [sv-ac] Re: R58c - access to past values ... with enable
From: Bassam Tabbara (bassam@novas.com)
Date: Fri Sep 20 2002 - 11:51:46 PDT

The semantics should be clear after I described the sampling i.e. along the lines of doing in rough OVA (you can refer to OVA semantics):

event the_clk: posedge(clk) && clk_en;       // there is another thread discussion on synchronous/asynchronous

clock matched(the_clk) {           // dunno if this is allowed, but in theory seems right

    .... = past(expr, 1)   // prev(expr, 1)

}

-Bassam.

Joseph Lu wrote:

So, what is your semantics of evaluating this event expression?

  prev(expr, 1)@(posedge (clk) && clk_en)

--Joseph

>Date: Fri, 20 Sep 2002 11:26:02 -0700 (PDT)
>From: Joseph Lu <Juin-Yeu.Lu@sun.com>
>Subject: Re: [sv-ac] Re: R58c - access to past values ... with enable
>To: Juin-Yeu.Lu@sun.com
>MIME-Version: 1.0
>Content-MD5: iPNL0SFhlcoW2dP/5DtlYA==
>
>Who's talking about Verilog ? prev ??? Yes as I said this is an event expression so in a pseudo
>assertion description
>sync the_clk: posedge(clk) && clk_en
>
>prev(expr, 1)@@(the_clk) in some way/shape or form (DAS/OVA/PSL...)
>
>-Bassam.
>
>Joseph Lu wrote:
>
>  >Date: Thu, 19 Sep 2002 15:08:27 -0700
>  >From: Bassam Tabbara <bassam@novas.com>
>  >X-Accept-Language: en
>  >MIME-Version: 1.0
>  >To: Adam Krolnik <krolnik@lsil.com>
>  >CC: Cindy Eisner <EISNER@il.ibm.com>, sv-ac@eda.org
>  >Subject: [sv-ac] Re: R58c - access to past values ... with enable
>  >Content-Transfer-Encoding: 7bit
>  >X-OriginalArrivalTime: 19 Sep 2002 22:08:27.0227 (UTC) FILETIME=[146AE2B0:01C26029]
>  >
>
>  >Adam,
>  >
>  >Thx for the example, 2 things.
>  >
>  >1) I think you are making a statement about -sampling-, so as I said earlier, I do not see
why
>this is limited
>  >to "prev", you are giving one example using that construct, if
>  >there is an enhancement to sampling I'm sure there are other examples of this symptom.
>  >2) In the example, I'm afraid I don't see why doing:
>  >
>  >.... prev(expr, 1)@(posedge (clk) && clk_en) does not do what you want to do for:
>
>  I am wondering if Verilog allow you to do @(posedge (clk) && clk_en). It is an event
>expression.
>  The only operator to compose two event expressions is or.
>
>  --Joseph

-- 
Dr. Bassam Tabbara
Technical Manager, R&D

Novas Software, Inc.
bassam@novas.com
(408) 467-7893
 

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