P1076 May 23, 2013 Meeting Minutes

Attendees:

• Not held
• Login to get the Dial-in Information

Agenda:

• Review VHDL-2008-MP remaining list items
• Review VHDL-2008-TBV 6, 9, and 13
• Check closure on AI from review lists.
• See these items in the collected requirements list

Review of VHDL-2008-MP

• MP6: Allow attribute declarations in code regions (not just declaration regions)
  • discussion
• MP8 - Make transport the default delay model
  • discussion
• MP - Allow subprogram bodies in package declarations
  • discussion
• MP - Ability to apply register kind semantics to std_logic. Retain last resolved value when all drivers are off
  • discussion
• MP - Remove white space requirement in physical literals
  • discussion
• MP - Short alias name for std_logic_vector
  • discussion
• MP - Value folding of std_ulogic (2 state/4 state)
  • discussion
• MP - Implicit generic/port map in component instance
  • have proposal for Implicit Parameter and Port Connections
  • discussion
• MP - Add Endif (like elsif)
  • discussion
• MP - One_hot assertion to remove priority from if-then-elsif
  • discussion
• MP - Longest static prefix issue with loops
  • discussion

Topic

• Discussion

Review and Approve Meeting Minutes:

• Motion: 2nd:

Next Meeting Date (proposed):

Thursday June 13, 8 am Pacific