Describe Timing Constraints

Proposal Details

  • Who Updates: DanielKho, <Add YourName>
  • Date Proposed: 2015-01-01
  • Date Last Updated:
  • Priority:
  • Complexity:
  • Focus:

Current Situation

There is currently no standardized way to specify timing constraints from behavioral models. The Synopsys Design Constraints (SDC) format is a de-facto industry standard, but these constraints are applied as separate (non-HDL) files, which will later get applied during synthesis or placement-and-routing of the design.

Requirement

[In progress...]

Specify a standard way to describe timing constraints similar to SDC, but directly from the behavioral model (VHDL). Some of these constraints include:

  1. Specifying false paths.
  2. Specifying multicycle paths.
  3. Specifying clocks (period, duty cycle).
  4. Setting delays on input and output ports.
  5. Specifying input drive strengths (capacitance, slew rate/transition time).
  6. Specifying output loading (capacitance, slew rate/transition time).
  7. Specifying interconnect parasitics (pin / net capacitance or loading).
  8. Specifying maximum and minimum constraints (path delays, drive strengths, capacitive loadings, parasitics).
  9. Describing clock uncertainty (jitter).

Propose to standardize several predefined VHDL attributes for this purpose.

Implementation details

[In progress...]

The idea is to use a consistent method of decorating a signal, and consistent ways of making signal assignments for the signal.

Code Examples

[In progress...]

signal clk:std_ulogic:='0';
attribute period:time; attribute period of clk:signal is 10 ns;
attribute maxTransition:time; attribute maxTransition of clk:signal is 1.5 ns;
...
clk <= not clk after clk'period/2;

This is equivalent to setting the SDC constraints:

create_clock -name clk -period 10 [get_nets clk]
set_clock_transition -max 1.5 [get_clocks clk]

Use Cases

Arguments FOR

Arguments AGAINST

General Comments

Supporters

Add your signature here to indicate your support for the proposal

-- DanielKho - 2015-01-01


This topic: P1076 > WebHome > Vhdl2019CollectedRequirements > TimingConstraints
Topic revision: r3 - 2020-02-17 - 15:34:39 - JimLewis
 
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