type spi_master_r is record mosi : std_logic; -- Data from master to slave miso : std_logic; -- Data from slave to master sclk : std_logic; -- Serial clock ssel : std_logic_vector -- Chip selects (active-low) end record spi_master_r; port view master of spi_master_r is mosi => out; miso => in; sclk => out; ssel => out; end port view master; could be combined using port syntax: type spi_master_r is port record mosi : out std_logic; -- Data from master to slave miso : in std_logic; -- Data from slave to master sclk : out std_logic; -- Serial clock ssel : out std_logic_vector -- Chip selects (active-low) end port record 'record to extract record declaration 'reverse/... to reverse 'in for input only - ie: monitor port view master2 of spi_master_r'record is -- ... end port view; attribute to_string : string; attribute to_string of std_logic : type is myFunc(10); attribute to_string of std_logic : type is myFunc[std_logic return string]; alias foo is myFunc[integer return string]; signal clock : std_logic; process begin report myfunc(clock); report std_logic'to_string(clock); end process;