Re: VHDL-AMS PLI and a Question about the Simulation Cycle

From: Ernst Christen <Ernst.Christen_at_.....>
Date: Thu Jan 04 2007 - 11:01:35 PST
Sameer,

Step a) defines that "The analog solver is executed." Therefore, the analog solver
executes at the beginning of each simulation cycle. Clause 12.6.6 then defines the actions
that the analog solver takes when it executes. These actions depend on the result of step
g) and other steps, more specifically whether the break flag is set and, to some extent,
whether this is a delta cycle or not.

Ernst Christen

On Thu, 4 Jan 2007 10:23:07 -0500, Sameer Kher wrote:
> Also, I was seeking a clarification on the simulation cycle as described
> in the LRM. My question is related to step (g) where the next simulation
> time is determined. The text says that the next simulation cycle "...is
> determined by setting it to the earliest of :
> - The value of type universal_time corresponding to TIME'HIGH
> - The next time at which a driver becomes active, or
> - The next time at which a process resumes..."
> Does this imply that the analog solver must execute at every digital
> event?
>
> Thanks,
> Sameer Kher
> R&D Engineer
> Ansoft Corp.


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