Re: Question on encryption

Hi Arpad,

Encryption is a topic that comes up from time to time. The issue is not specific to 
VHDL-AMS, but affects also VHDL (IEEE Std 1076). A proposal has been submitted to the VHDL 
Analysis and Standardization Group (VASG) to support encryption in a VHDL text. You can 
find some information about the topic by following the VHDL-200x link under P1076 at 
eda.org. Go to Old VHDL-FT documents, near the bottom there are links to relevant 
documents. There is also a presentation at 
http://www.accellera.org/apps/group_public/download.php/118/VHDL_IP_Encryption.ppt.

Thanks.
Ernst Christen

On Mon, 24 Apr 2006 11:25:32 -0700, Muranyi, Arpad wrote:
> Hello everyone,
>
> Sorry for bringing up such off topic questions all the time,
> but I would like to find out whether encryption has been
> considered by the workgroup for VHDL-AMS models.
>
> The reason I am asking is because this has been brought up
> in the recent IBIS Open Forum discussions in connection
> with modeling bleeding edge high speed buffers behaviorally.
> Semiconductor vendors feel increasingly uneasy about
> releasing even behavioral models for such buffers without
> encryption.  In addition we do not like the idea of using
> the individual and proprietary encryption schemes of EDA
> vendors, because that would require the model makers to
> encrypt the same model multiple times for each tool.  It
> seems that there is a strong need for some sort of a tool
> independent encryption scheme.
>
> We thought we should look around what has been done, if
> anything, before we reinventing the wheel.
>
> Thanks,
>
> Arpad
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