Re: Question on encryption

Arpad,

VHDL 1076 is being enhanced by Accellera this year.  One the expected 
enhancements is an encryption model for IP at the lexical level of 
source code.  My expectation is that this will serve this need quite 
well. (There is a path to that becoming a part of IEEE 1076 and being 
incorporated into products, of course.)  It is architecturally quite 
language neutral and serves equally well for Verilog and is part of the 
latest 1364 standard already. 1076.1 should strongly consider it before 
reinventing anything.

Regards,
John Shields

Muranyi, Arpad wrote:
> Hello everyone,
>
> Sorry for bringing up such off topic questions all the time,
> but I would like to find out whether encryption has been
> considered by the workgroup for VHDL-AMS models.
>
> The reason I am asking is because this has been brought up
> in the recent IBIS Open Forum discussions in connection
> with modeling bleeding edge high speed buffers behaviorally.
> Semiconductor vendors feel increasingly uneasy about
> releasing even behavioral models for such buffers without
> encryption.  In addition we do not like the idea of using
> the individual and proprietary encryption schemes of EDA
> vendors, because that would require the model makers to
> encrypt the same model multiple times for each tool.  It
> seems that there is a strong need for some sort of a tool
> independent encryption scheme.
>
> We thought we should look around what has been done, if
> anything, before we reinventing the wheel.
>
> Thanks,
>
> Arpad
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