Subject: Re: Definition for matrices in VHDL-AMS
From: Steve Grout (sgrout@tality.com)
Date: Tue Dec 12 2000 - 06:22:49 PST
All - re matrices vs current 1-dimension real arrays, if we are discussing
what next needs done then to VHDL-AMS, this would certainly be one issue
(with apologies to any preceding discussion/work which led to a
scope of only one dimension objects).
Real hardware is, of course, FULL of cases of 2 and 3 dimensional arrays.
And certainly at any point in the life cycle of a design, the target design
often requires such a facility to crisply describe the specification,
the requirements, the constraints, the intent, the system level, the
subsystem level, the working RTL level, and low level building blocks
from which the design is implemented.
At times, ANY part of the design may benefit from having the facility
of PACKAGE with which to separate out an aspect of the design for
separate definition and possible reuse. The below example is of course
an important example of using PACKAGE to isolate an existing language
limitation in the course of defining an extension to the language
and/or providing a specific design facility not directly available!
But its very important that the language has facilities that we
can use directly, i.e., describe hardware, its algorithms, and structure,
and in this case especially analog and mixed signal target hardware.
I personally also know of no native aspect of electronic hardware that
might lead us to concluding that we are better off with only having
1 dimensional constructs with which to design.
So I would urge we, at some point, move to include full array capability
within the scope of VHDL-AMS.
> Walter Commerell wrote:
> >
> > Hello,
> > we're working on a VHDL-AMS compiler to Matlab/Simulink. For this there
> > are some questions. Can anybody give an answer?
> > Is VHDL-AMS case sensitive? Where is it in the LRM?
My only comment here is that this is a trivial adjustment to a compiler
LEX facility so that in the long term, we should be moving towards a
common practice with
- long term direction of VHDL overall
- closure with the practice used within Verilog
- closure with practices for modern system and software
implementation languages, including ALC, SLDL, C/C++, Java, etc.
I personally find case sensitivity to be a Very_Useful_Tool but I accept
that may just be due my own experience in design and EDA.
--Steve Grout
-- Steve Grout - Senior Methodology Consultant Tality Analog/Mixed-Signal Design Services 200 Regency Forest Drive - Suite 260, Cary, NC 27511 PAGER: 888-811-5819 or 8115819@pagemci.com EMAIL sgrout@tality.com, Phone 919-481-6844, FAX 919-380-3902> No. See 13.3.1 and 13.9 of the LRM. > > > Is there a definition in the actual VHDL-AMS language for matrices to > > describe the following example? > > How can elements of a matrix accessed? > > I'm not sure whether this fully answers your question. Only one > dimensional real arrays are defined in VHDL-AMS. You would have to write > a package: > > PACKAGE Matrix IS > TYPE real_matrix IS ARRAY (natural RANGE <>, natural RANGE <>) OF > real; > FUNCTION "*" (l: real_matrix; r: real_vector) RETURN real_vector; > FUNCTION "*" (l: real_vector; r: real) RETURN real; > END PACKAGE Matrix; > > PACKAGE BODY Matrix IS > -- include definitions of "*" here > END PACKAGE BODY Matrix; > > (I don't recall if "*" is already defined for real_vector * real. I > don't have the LRM to hand!) > > The rest of your example becomes: > > USE work.Matrix.ALL; > ENTITY StateSpace IS > GENERIC (a,b : real_matrix; > c,d : real_vector); > PORT (QUANTITY u: IN real_vector; > QUANTITY y: OUT real); > END ENTITY StateSpace; > > ARCHITECTURE abcd OF StateSpace IS > QUANTITY x: real_vector(a'range(1)); > BEGIN > x'dot == a*x + b*u; > y == c*x + d*u; > END ARCHITECTURE abcd; > --------------------------------------------- > > USE work.Matrix.ALL; > ENTITY testbench IS > END ENTITY testbench; > > ARCHITECTURE statespace OF testbench IS > QUANTITY u: real_vector(1 TO 2); > QUANTITY y: real; > BEGIN > s: ENTITY Work.StateSpace(abcd) > GENERIC MAP (a => ((0.12, 2.0), (3.0, 1.5)), > b => ((2.0, 7.0), (3.0, 1.0)), > c => (0.1, 2.0), > d => (0 TO 1 => 0.0)) > PORT MAP (u => u, y => y); > u == (now, sin(now)); > END ARCHITECTURE statespace; > > Mark > -- > =================================================================== > Dr Mark Zwolinski > Electronic System Design Group Tel. (+44) (0)23 8059 3528 > Dept. of Electronics & Computer Science Fax. (+44) (0)23 8059 2901 > University of Southampton Email. mz@ecs.soton.ac.uk > Southampton SO17 1BJ, UK http://www.ecs.soton.ac.uk/~mz
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