Re: Definition for matrices in VHDL-AMS


Subject: Re: Definition for matrices in VHDL-AMS
From: Mark Zwolinski (mz@ecs.soton.ac.uk)
Date: Tue Dec 12 2000 - 04:45:43 PST


Walter,

Walter Commerell wrote:
>
> Hello,
> we're working on a VHDL-AMS compiler to Matlab/Simulink. For this there
> are some questions. Can anybody give an answer?
> Is VHDL-AMS case sensitive? Where is it in the LRM?

No. See 13.3.1 and 13.9 of the LRM.

> Is there a definition in the actual VHDL-AMS language for matrices to
> describe the following example?
> How can elements of a matrix accessed?

I'm not sure whether this fully answers your question. Only one
dimensional real arrays are defined in VHDL-AMS. You would have to write
a package:

    PACKAGE Matrix IS
      TYPE real_matrix IS ARRAY (natural RANGE <>, natural RANGE <>) OF
real;
      FUNCTION "*" (l: real_matrix; r: real_vector) RETURN real_vector;
      FUNCTION "*" (l: real_vector; r: real) RETURN real;
    END PACKAGE Matrix;

   PACKAGE BODY Matrix IS
   -- include definitions of "*" here
   END PACKAGE BODY Matrix;

(I don't recall if "*" is already defined for real_vector * real. I
don't have the LRM to hand!)

The rest of your example becomes:

    USE work.Matrix.ALL;
    ENTITY StateSpace IS
      GENERIC (a,b : real_matrix;
               c,d : real_vector);
      PORT (QUANTITY u: IN real_vector;
            QUANTITY y: OUT real);
    END ENTITY StateSpace;

    ARCHITECTURE abcd OF StateSpace IS
        QUANTITY x: real_vector(a'range(1));
    BEGIN
        x'dot == a*x + b*u;
        y == c*x + d*u;
    END ARCHITECTURE abcd;
---------------------------------------------

    USE work.Matrix.ALL;
    ENTITY testbench IS
    END ENTITY testbench;

    ARCHITECTURE statespace OF testbench IS
        QUANTITY u: real_vector(1 TO 2);
        QUANTITY y: real;
    BEGIN
        s: ENTITY Work.StateSpace(abcd)
                GENERIC MAP (a => ((0.12, 2.0), (3.0, 1.5)),
                             b => ((2.0, 7.0), (3.0, 1.0)),
                             c => (0.1, 2.0),
                             d => (0 TO 1 => 0.0))
                PORT MAP (u => u, y => y);
        u == (now, sin(now));
    END ARCHITECTURE statespace;

Mark

-- 
===================================================================
Dr Mark Zwolinski 
Electronic System Design Group           Tel. (+44) (0)23 8059 3528   
Dept. of Electronics & Computer Science  Fax. (+44) (0)23 8059 2901
University of Southampton                 Email. mz@ecs.soton.ac.uk
Southampton SO17 1BJ, UK             http://www.ecs.soton.ac.uk/~mz



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