1. Language enhancements that ease the job of the verification engineer
2. Modeling DUV environment and I/O
3. Consider coverage and assertions implications

Much of the work for this group will be done via the email reflector and teleconferences.  Meeting dates will be announced on the reflector.  Start date should be March / April, 2003.

Send an email message majordomo@eda.org with subscribe vhdl-200x-tbv in the message body (or use the link below).  You must join the reflector before you can post to it.

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