[vhdl-200x-ft] Fixed_Pkg and constrained subtypes

From: Jim Lewis <jim_at_.....>
Date: Tue Mar 08 2005 - 17:05:35 PST
A15  NONE        Jim          Send to David FP literals & updates used named subtypes

I have the above action to demonstrate use of named subtypes
to help simplify some of the subprograms in fixed_pkg and
use of literals.

1.0 Literal problem
===============================
With the types sfixed/ufixed each index location has a
weight.  Because of this, use of string literals is
difficult as the range cannot just be randomly picked.

1.1 Use a Subtype
----------------------------
One potential methodology solution to this problem is to
use a named subtype to qualify the size of the literal.
For example:

   subtype ufixed_8_2 is ufixed (7 downto -2) ;
   subtype ufixed_9_2 is ufixed (8 downto -2) ;
   signal  A : ufixed_8_2 ;
   signal  Y : ufixed_9_2 ;

   Y <= A + ufixed_8_2'(B"0000_0101_10") ;   --  A + 5.5

Of course there are lots of other potential solutions
for people who prefer to work with binary literals.

1.2 Use a constant
----------------------------
   subtype ufixed_8_2 is ufixed (7 downto -2) ;
   subtype ufixed_9_2 is ufixed (8 downto -2) ;
   signal    A : ufixed_8_2 ;
   Constant  C5_5 : ufixed_8_2 := "0000_0101_10" ;
   signal    Y : ufixed_9_2 ;

   Y <= A + C5_5 ; --  A + 5.5

1.3  Use a real number
----------------------------
   subtype ufixed_8_2 is ufixed (7 downto -2) ;
   subtype ufixed_9_2 is ufixed (8 downto -2) ;
   signal    A : ufixed_8_2 ;
   signal    Y : ufixed_9_2 ;

   Y <= A + 2#00000101.10# ; A + -- 5.5

   Of course for high precision math, VHDL's implementation of
   real may impact the actual bits from the above real literal.


2.0 Subprograms in fixed_pkg
--------------------------
In fixed_pkg, both positive and negative indicies are used.
Furthermore, for types sfixed and ufixed, each index now
has a weight.  This is different from the type signed and
unsigned where all indicies are positive and the left most
bit is the sign bit or most significant bit.

In fixed_pkg, there are a number of subprograms of the
following form:

   -- Type cast a "unsigned" into a "ufixed", used internally
   function to_fixed (
     arg                  : UNSIGNED;        -- shifted vector
     constant left_index  : INTEGER;
     constant right_index : INTEGER)
     return ufixed is
     variable result : ufixed (left_index downto right_index);
     variable j      : INTEGER := arg'high;  -- index for arg
   begin  -- function to_fixed
--    result := ufixed(arg);
     floop : for i in result'range loop
       result(i) := arg(j);                  -- res(4) := arg (4 + 3)
       j         := j - 1;
     end loop floop;
     return result;
   end function to_fixed;

The following are my untested re-write of some
of these using named subtypes:

   -- Type cast a "unsigned" into a "ufixed", used internally
   function to_fixed (
     arg                  : UNSIGNED;        -- shifted vector
     constant left_index  : INTEGER;
     constant right_index : INTEGER
   ) return ufixed is
     subtype result_subtype is ufixed (left_index downto right_index);
   begin  -- function to_fixed
     return result_subtype(arg);
   end function to_fixed;


   -- Type cast a "signed" into an "sfixed", used internally
   function to_fixed (
     arg                  : SIGNED;          -- shifted vector
     constant left_index  : INTEGER;
     constant right_index : INTEGER
   ) return sfixed is
     subtype result_subtype is sfixed (left_index downto right_index);

   begin  -- function to_fixed
     return result_subtype(arg);
   end function to_fixed;

   -- Type cast a "ufixed" into an "unsigned", used internally
   function to_uns (
     arg : ufixed                       -- fp vector
   ) return UNSIGNED is
     subtype result_subtype is UNSIGNED (arg'high - arg'low downto 0);
   begin  -- function to_uns
     return result_subtype(arg);
   end function to_uns;


Cheers,
Jim
-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Received on Tue Mar 8 21:00:06 2005

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