RE: [vhdl-200x-ft] Implicitly referencing std.textio and library IEEE

Steve Bailey said it best:
<Let's not all forget the context:>
Ben: Back then, the guarded blocks were not popular, and 1164 came into being, and was popular. Making 1164 and textio part of "the core" does not add any extra baggage because those types and methods will be introduced by the compiler only when needed.
Note that package "standard" is part of the core, and it is not necessary to add at the front of every entity or package declaration "library std; use std.standard.all;". So why not integrate the 1164 and textio, and even the floating point packages as part of the core?

<5. With context units, the most a user must do is explicitly reference
the context unit to get the library and use clauses for all that they
need. It was also my desire to see the LRM allow tools a mechanism by
which the specification of a default context clause could be specified
and automatically applied just ast library STD and use STD.STANDARD.all
are implicit today.>

Ben: I did not follow the idea of "context", but it sounds similar to a Verilog "include".
If it is a defaulted context, then I'll buy it.

<In summary, I believe if we are to address the convenience benefit, we
should do so via context units and an ability to specify a default
context unit. This will ensure backward compatibility with all existing
VHDL code.>
Great if 1164, textio, and floating point packages can be the defaults.

> I really understand this point of view.
> However, this point of view break the VHDL spirit.
> VHDL and Verilog are two opposites way to handle features:
>
> Verilog:
> * a bag of anything (unless I am wrong); no real structure.
No war here. But many successful designs were implemented in both HDLs.
Linting tools, for both HDLs have helped iron out coding errors.
BTW, SystemVerilog has introduced several types that are in VHDL (e.g., enu, structure, multi-dimensional arrays) + classes. My point in mentioning Verilog was that the core included everything, and users do not need to import packages to access things that are defined in the LRM.

>
> VHDL:
> * a core: 1076
> * additionnal packages: 1164, 1076.x
Thus, you are saying that the additional packages are part of the LRM, but not part of the core. I don't like that!

> Each time a feature has to be added in Verilog, it is added
> in the core.
> Therefore the core is huge and difficult to read.
Separating the core from additional packages does not ease the situation!

 
> Furthermore, not everyone want to use ieee.std_logic_1164.
> Think about people who just use bit/bit_vector, or AMS-VHDL.
Bits are are in the core.
AMS-VHDL, addresses the analog aspect. Since this group is not addressing that, users can introduce their own packages. I would have no objection in making that part of the core if there are no issues. I am not really familiar with AMS.

>
> For your user on comp.lang.vhdl, I have two comments:
> * He should use a good editor/IDE, which may automatically
> add the context clauses.
> * He surely doesn't understand VHDL beyond basic feature, and
> in this case, Verilog may be better for him.

I use emacs, a great vhdl editor! But that is not the issue. The core in any language should include the complete dictionary of what users need. VHDL is mature enough by now, and we know what engineers are currently using.
By the way, 1076.6 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis
is used in conjunction with IEEE Std 1076.3TM-1997, IEEE Standard Synthesis Packages (NUMERIC_BIT and NUMERIC_STD), which should be part of the core.

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* Component Design by Example ", 2001 isbn 0-9705394-0-1
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Received on Mon Dec 20 12:49:39 2004