RE: [vhdl-200x-ft] Question on FT14: why a period in array elemen t constraint

From: Hinton, Ryan W @ CSW-SLC <@>
Date: Mon Dec 20 2004 - 07:53:18 PST

Peter,

The period was included to make it more consistent with FT-15, which has
been deferred. The syntax for the constraint is a little odd, but in FT-15
the period was used to slice multiple levels of hierarchy (as opposed to
slicing the top-level array multiple times).

---
Ryan Hinton
L-3 Communications / Communication Systems - West
ryan.w.hinton@L-3com.com
-----Original Message-----
From: Peter Ashenden [mailto:peter@ashenden.com.au]
Sent: Wednesday, December 15, 2004 10:00 PM
To: vhdl-200x-ft@eda.org
Subject: [vhdl-200x-ft] Question on FT14: why a period in array element
constraint
Folks,
I'm looking through FT14, and wonder why the proposed syntax includes a
period before an array element constraint.  The specific rule is
  augmented_index_constraint ::=
    optional_index_constraint . constraint
This means a subtype indication constraining an element subtype would be
written
  A(0 to 7).(10 downto 1)
Is there any reason for not omitting the period and just writing it as
  A(0 to 7)(10 downto 1)
Thanks.
Cheers,
PA
--
Dr. Peter J. Ashenden                        peter@ashenden.com.au
Ashenden Designs Pty. Ltd.                   www.ashenden.com.au
PO Box 640                                   Ph:  +61 8 8339 7532
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Received on Mon Dec 20 07:53:38 2004

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