RE: [vhdl-200x-ft] Fixed Point and array representation

Ryan,

The use of records does change the situation. Sure there are corner cases where it is valid to wonder if it makes sense (such as using a null array for integer or fractional part). However, what it does accomplish is removal of the use of the sign of the index to indicate which is the integer and which is the fractional part of the value. In the record case, as long as the number of bits for each is the same, the assignment is legal and it really doesn't matter what the index range is.

The record approach is clearly superior in my opinion. The problem is that it depends on a new capability which means synthesis tools must support at least that VHDL-200x enhancement in order to support the fixed point package.

-Steve Bailey

> -----Original Message-----
> From: owner-vhdl-200x-ft@eda.org
> [mailto:owner-vhdl-200x-ft@eda.org] On Behalf Of Hinton, Ryan
> W @ CSW-SLC
> Sent: Monday, July 26, 2004 12:12 PM
> To: 'Jim Lewis'; vhdl-200x-ft@eda.org
> Subject: RE: [vhdl-200x-ft] Fixed Point and array representation
>
> Actually, the situation is even worse for representing values
> with the binary point outside of the value. Here is the
> current approach:
>
> signal A : ufixed(-1 downto -4) ;
> signal Y : ufixed(-2 downto -5) ;
>
> The following is still legal, although we want it not to be:
> Y <= A ;
>
> Moving to a record type does not solve the problem:
> type ufixed is record
> N : unsigned ;
> F : unsigned ;
> end record ;
>
> signal rA : ufixed(N(-1 downto 0), F(3 downto 0)) ;
> signal rY : ufixed(N(-2 downto 0), F(3 downto 0)) ;
>
> -- still legal because all null arrays are equivalent (right?)
> rY <= rA;
>
> The most natural way to represent what we're trying to do
> with fixed point values requires multi-mode unconstrained
> records to synthesize efficiently:
> type ufixed is record
> num : unsigned ;
> constant exp : integer ;
> end record ;
>
> I think the current fixed point proposal is a step in the
> right direction, but I want to add this information to Jim's
> logged issue.
>
> ---
> Ryan Hinton
> L-3 Communications / Communication Systems - West
> ryan.w.hinton@L-3com.com
>
>
> -----Original Message-----
> From: Jim Lewis [mailto:Jim@SynthWorks.com]
> Sent: Friday, July 16, 2004 3:24 PM
> To: vhdl-200x-ft@eda.org
> Subject: [vhdl-200x-ft] Fixed Point and array representation
>
>
> At the last FT meeting, we talked about fixed point
> representation as an array and sizing rules.
>
> After the meeting, Steve pointed out a limitation that I
> wanted to log. When we do an assignment with the array
> representation, all we can ensure is that the array sizes are
> the same and we cannot ensure that the number and fraction
> are appropriate sizes.
>
> To best see this, consider the following:
> signal A : ufixed(7 downto -3) ;
> signal Y : ufixed(6 downto -4) ;
>
> The following is legal:
> Y <= A ;
>
>
> On the other hand,
> if we were to make ufixed a record with unconstrained arrays
> (proposed language feature), we could avoid this
> part:
> type ufixed is record
> N : unsigned ;
> F : unsigned ;
> end record ;
>
> signal rA : ufixed(N(7 downto 0), F(2 downto 0)) ;
> signal rY : ufixed(N(6 downto 0), F(3 downto 0)) ;
>
> Now the following is illegal:
> -- rY <= rA ; -- Illegal
>
> This more closely matches the nature of VHDL.
> However, it would present issues with testing (feature not
> available yet) and it would not be synthesizable until the
> new features were implemented.
>
> I am not leaning one way or the other, I just wanted to log the issue.
>
> Best Regards,
> Jim
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis
> Director of Training mailto:Jim@SynthWorks.com
> SynthWorks Design Inc. http://www.SynthWorks.com
> 1-503-590-4787
>
> Expert VHDL Training for Hardware Design and Verification
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
Received on Wed Jul 28 23:08:41 2004