[vhdl-200x-ft] RE: Multi-dimensional and multi-level slices

(Ryan sent this question to me, I'm responding to the entire fast-track
reflector)

>We met briefly at the VHDL-200x meeting at DAC last month.
>You mentioned
>something about problems with multi-dimensional and/or
>multi-level slices in
>sensitivity lists. What are the issues you are aware of?
>
>I think we're scheduled to discuss this proposal at the next telecon
>(Monday, 19 July), so I'm very interested in any comments or
>suggestions
>ahead of time.

Multi-level slices pose a problem of efficiency in implementation that
effect both simulation performance and memory. It arises from creating
large sensitivity lists where the elements are not continguous in
memory.

(Pardon any syntax problems below, I'm on vacation and doing this
quickly)

Lets say you are using a 65-bit wide vector to represent a 64-bit number
follow by an LSB that is the parity of the previous 64 bits. Then you
want to have a process that wakes up on changes in the parity bit.

        type bit_65_type is array (65 downto 1, 1 to 1000) of bit;

        signal bit_65 : bit_65_type;

Now if you say something like:

        wait on bit_65(1, 1 to 1000);

You've put 1000 items on the sensitity list of the process. Note that
these are not contiguous in memory. This leads to having a huge list in
the simulator that you need to walk down to find if the interesting bit
changes. This list takes up memory and the walk takes up time.

When only the last element can be sliced then the simulator can just
test if a value update is in a range of addresses which is much more
efficient.

Note this purely an implementation concern and if users really need this
expression then I have no real objection, they should just be aware that
they may hammer performance by using a very brief syntax to specify
possibly HUGE sensitivity lists.

Jay

===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================

>-----Original Message-----
>From: Hinton, Ryan W @ CSW-SLC [mailto:ryan.w.hinton@L-3com.com]
>Sent: Wednesday, July 14, 2004 7:57 PM
>To: Jay Lawrence
>Subject: Multi-dimensional and multi-level slices
>
>Jay,
>
>We met briefly at the VHDL-200x meeting at DAC last month.
>You mentioned
>something about problems with multi-dimensional and/or
>multi-level slices in
>sensitivity lists. What are the issues you are aware of?
>
>I think we're scheduled to discuss this proposal at the next telecon
>(Monday, 19 July), so I'm very interested in any comments or
>suggestions
>ahead of time.
>
>Thanks!
>
>---
>Ryan Hinton
>L-3 Communications / Communication Systems - West
>ryan.w.hinton@L-3com.com
>
>
Received on Fri Jul 16 05:08:18 2004