[vhdl-200x-ft] Discussion: FT10 Conditional Assignment & Ternary operator

Request for Comments & Discussion on FT10

Please note, this is a request for comments (not votes)
so all (meaning non-members) are welcome to comment.

FT10 Includes:
   A) Conditional assignment for sequential assignments.
   B) Selected signal assignment for sequential assignments.
   C) Ternary Expressions.

The full proposal is at:
http://www.eda-twiki.org/vhdl-200x/vhdl-200x-ft/proposals/ft10_assignment_ternary.pdf

Currently A & B are only available for signals in a
concurrent context. The proposal expands this syntax
to allow both signals and variables to use this syntax
in a sequential context (process or subprogram).

For a Moore type statemachine (or state), it is
very tempting to want to write the following for
the present state to next state description:
   NextState <= FLASH when (FP = '1') else IDLE ;

Currently the language requires the more verbose syntax:
   if (FP = '1') then
     NextState <= FLASH ;
   else
     NextState <= IDLE ; 30
   end if ;

After I initially proposed A&B, it was requested that
the conditional form be available in a wider context
such as initialization. This requires a ternary
expression:
   Signal A : integer := 7 when GEN_VAL = 1 else 15 ;

During the review of this proposal at the DAC VHDL-200X
meeting and previous reflector discussions, there was
some concern raised over:
1) Can conditional signal assignments be moved into a
     sequential scope?
2) Do we need a ternary expression?
3) Should the ternary expression have the same syntax as
     conditional signal assignment? Will this cause
     confusion (amoung users)?
4) Is a ternary expression overloadable?
5) How would you rank the different aspects of the proposal?
     1) Conditional assignment for sequential assignments.
     2) Selected signal assignment for sequential assignments.
     3) Ternary Expressions.
6) Can the ternary expression have the same syntax
     as conditional signal assignment?
     Is the BNF ok for a compiler?

Note, these concerns were addressed as general concerns.
Before commenting, please read the proposal:
http://www.eda-twiki.org/vhdl-200x/vhdl-200x-ft/proposals/ft10_assignment_ternary.pdf

I will address each of these here. My opinions are mine,
and do not necessarily represent the majority opinion of
the working group (WG), so if you agree (or disagree), it
is important that you comment. Also note that at this
point in time we are discussing/commenting and not voting.

------------- ------------- ------------- ------------- -------------
1) Can conditional signal assignments be moved into a
     sequential scope?

I think the concern here was over exectution/sensitivity list.
With conditional assignment in a process, execution of
the statement is controlled by the process and enclosing
control statements (if, case, loop, ...).

Should we do this? I think it is intuitive to use this
statement as shown in the first example above. I teach
VHDL and eventhough it in class we discuss that conditional
signal assignment is not permitted in a process, students
still try to do it. This proposal seeks to make what is
natural legal.

------------- ------------- ------------- ------------- -------------
2) Do we need a ternary expression?
It was specifically requested by VHDL users.
Another useful example (in a subprogram):
   constant max_len : integer := A'length when A'length > B'length else B'length ;

------------- ------------- ------------- ------------- -------------
3) Should the ternary expression have the same syntax as
     conditional signal assignment?
     Will this cause confusion?

My opinion is that if we introduce a ternary expression,
then it must have the same syntax as conditional signal
assignment and its usage must be consistent with
conditional assignment. One of the main features of VHDL
is its uniformity and consistency.

I believe that to create a ternary expression with different
syntax would be confusing. Furthermore syntax like ?: is not
as readable as the VHDL syntax, hence, does not carry the
spirit of VHDL.

The downside of ternary expressions is that it is possible to
create unreadable expressions with them. I have seen some
good examples of this. However, I think this would be an
argument against ternary expressions in general and not against
any particular ternary expression syntax.

------------- ------------- ------------- ------------- -------------
4) Is a ternary expression overloadable?

No. It is not an operator.

The proposal creates ternary expressions. Ternary expressions
return the value of the selected subexpression and as such
they are not overloadable.

------------- ------------- ------------- ------------- -------------
5) How would you rank the different aspects of the proposal?
     A) Conditional assignment for sequential assignments.
     B) Selected signal assignment for sequential assignments.
     C) Ternary Expressions.

I rank A #1. I would expect to use conditional assignment in
sequential assignments in many statemachines in my designs.

I rank C #2. I would expect to user ternary expressions
in some designs.

I rank B #3. I would expect to use this infrequently.
However, if we do A, I think it is necessary to do B to
maintain language consistency.

------------- ------------- ------------- ------------- -------------
6) Can the ternary expression have the same syntax
     as conditional signal assignment
     (meaning is the BNF ok for a compiler)?

If you know the BNF for conditional signal assignment,
you may have some concerns here. It would be easy to
make a mistake with the BNF. Because of this, the
proposal warrents a broad detailed review. I will preview
the approach I used in the proposal. For details see the
proposal.

I consider it desirable that ternary expressions
have the same syntax and usage as conditional waveforms.
As a result, ternary expressions need to have lower
precedence than any of the operators. Hence, they come
before logic operators in the BNF.

Note that in conditional signal assignment syntax there
are no parentheses around a conditional waveform.
This is key to distinguishing a conditional waveform
from a ternary expression.

In the proposed enhanced syntax, a ternary expression
is not allowed to occur in a signal assignment without
being enclosed in parentheses. This is accomplished
in the BNF by having a waveform element reference a
logical rather than an expression.

------------- ------------- ------------- ------------- -------------
Let the discussion begin.

Cheers,
Jim

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~