Subject: RE: Assertions Meeting
From: Stephen Bailey (SBailey@model.com)
Date: Wed Jun 18 2003 - 20:37:12 PDT
This is to confirm that we are on for the meeting (as stated below) at
Mentor Graphics (you can schedule your travel).
The Mentor web site has information on the location of the Mentor offices.
See http://www.mentor.com/corp_info/headquarters.html
<http://www.mentor.com/corp_info/headquarters.html> . There's a map if you
click on the "Directions" link for the Wilsonville headquarters.
As far as hotels, there are many around, especially a bit north on I-5. I
usually stay at the Hilton Garden Inn on Kruse Oaks in Lake Oswego. There's
also an Embassy Suites in Beaverton. I would avoid the Crowne Plaza on
Kruse Oaks in Lake Oswego. The hotel is fine. But, it is right off I-5.
So, if you are unlucky to get a room overlooking the freeway, you may have a
difficult time sleeping.
I can have lunch arranged for us for Wed and Thurs, or we can go out to eat
somewhere nearby. Let me know if you have a preference (and any dietary
considerations). I would lean towards going out at least one of either Wed
or Thurs. Our group will be small enough that we shouldn't encounter huge
delays and getting out of the room will be a nice break.
Speaking of group size, I'm assuming the following people will attend. If
you plan on attending and your name is not listed below, please send me an
email so I can plan accordingly.
Rob Anderson
Erich Marschner
Richard Wallace
Dennis Brophy
Tej Singh (?)
Stephen Bailey
It's a relatively small group, but a good size for getting real work done.
NOTE: This is a technical meeting and not a VASG/VHDL-200x Working Group
meeting. Anyone who is interested and motivated to work on assertion-based
verification enhancements for VHDL are welcome to come.
-Steve
I will hopefully be able to confirm the meeting by end of this week or early
next.
Details:
Where: Wilsonville, OR (Mentor Graphics)
When: 2.5 days, 9 - 11 July (1/2 day on friday 11 Jul)
Agenda:
- Overview of PSL. I'm hoping Erich Marschener or someone else will be
able to provide everyone with an overview of PSL.
- Integrating PSL with VHDL. What needs to be done other than eliminating
the comments for the embedded PSL use model. What technical issues there
might be.
- Any related language changes. For example, the request to allow reading
OUT mode ports was driven by ABV needs.
- Outline a technical proposal. I'm hopeful that we can generate the
outline for a technical proposal which we can then work in the succeeding
weeks/months.
----
Stephen A. Bailey
TME, Model Technology
1811 Pike Road, Building #2, Suite F
Longmont, CO 80501
sbailey@model.com
303-775-1655 (mobile)
720-494-1202 (office)
720-494-0457 (fax)
www.model.com
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