Subject: RE: Assertions Meeting
From: Erich Marschner (erichm@cadence.com)
Date: Wed Jun 18 2003 - 10:23:38 PDT
Steve,
I'm planning to attend the meeting. I can give an overview of PSL as you've suggested. I'd also like to talk about how PSL concepts could be added to VHDL, as an extension of the existing concurrent assertion statement.
Regards,
Erich
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Erich Marschner, Cadence Design Systems
Senior Architect, Advanced Verification
Phone: +1 410 750 6995 Email: erichm@cadence.com
Vmail: +1 410 872 4369 Email: erichm@comcast.net
-----Original Message-----
From: Stephen Bailey [mailto:SBailey@model.com]
Sent: Wednesday, June 18, 2003 1:07 PM
To: 'vhdl-200x-asr@eda.org'
Subject: Assertions Meeting
I will hopefully be able to confirm the meeting by end of this week or early next.
Details:
Where: Wilsonville, OR (Mentor Graphics)
When: 2.5 days, 9 - 11 July (1/2 day on friday 11 Jul)
Agenda:
- Overview of PSL. I'm hoping Erich Marschener or someone else will be able to provide everyone with an overview of PSL.
- Integrating PSL with VHDL. What needs to be done other than eliminating the comments for the embedded PSL use model. What technical issues there might be.
- Any related language changes. For example, the request to allow reading OUT mode ports was driven by ABV needs.
- Outline a technical proposal. I'm hopeful that we can generate the outline for a technical proposal which we can then work in the succeeding weeks/months.
----
Stephen A. Bailey
TME, Model Technology
1811 Pike Road, Building #2, Suite F
Longmont, CO 80501
sbailey@model.com
303-775-1655 (mobile)
720-494-1202 (office)
720-494-0457 (fax)
www.model.com
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