Define language support for temporal logic expressions and assertions.

Much of the work for this group will be done in conference calls and on the reflector.  Meeting dates will be announced on the reflector.  

A Meeting was held July 9 and 10 2003 in Portland Oregon. Meeting notes are available as a PDF file or as a Powerpoint Presentation.

The excellent presentation: "PSL for VHDL" by Erich Marschner from this meeting is now available as a PDF file.

A language change specification is now available for review and comment. This proposal provides an initial capability that provides basic temporal sequence, property, assertion, assume and cover capabilities from PSL to VHDL. It is expected that this will be a first level of integration and that additional work more further exploiting PSL capabilities will be considered for the planned 2nd language revision under the VHDL-200x effort. The PDF is located here.

There is also a proposal to extend VHPI to handle PSL as well. Cadence has provided this as a donation to the WG. The PDF for the VHPI PSL extensions is here.

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