On 17 April 2015 at 04:17, Dhiraj Kumar Prasad < dhiraj.kumar.prasad@xilinx.com> wrote: > > <snip> > standard.vhd: > type BOOLEAN_VECTOR is array (INTEGER range <>) of BOOLEAN; > type BIT_VECTOR is array (INTEGER range <>) of BIT; > type INTEGER_VECTOR is array (INTEGER range <>) of INTEGER; > type REAL_VECTOR is array (INTEGER range <>) of REAL; > type TIME_VECTOR is array (INTEGER range <>) of TIME; > > [dhiRAj]: Yes, I don’t see any harm in this rather it will give increase > the memory size by 2X( integer range ~= 2 of natural range) > I think in the end, the designer has to constrain the ranges. So if the lengths are the same, I feel there shouldn't be much increase in memory requirements for compilers? For example, the following two expressions should use the same amount of compiler memory? signal s0: boolean_vector(0 to 8); signal s1: boolean_vector(-4 to 4); -- assuming negative indices are permitted > [dhiRAj] Do we want to go from strict type check to relax type check like > System Verilog? I assume that we don’t want to relax type checking so > instead of going for implicit, we can have conversion function for this. > > Yes, I don't mind conversion functions, such as the TO_XXX() functions as mentioned by Woody. > > > Best regards, > > Daniel > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sat Apr 18 00:50:37 2015
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