RE: {Spam?} Re: [vhdl-200x] VHDL-2008: Records and aggregates

Hi,

Defining an anonymous type should not be encouraged as VHDL being a strict type check, restrict the usage. You can still use this type RNG_BYTE2  as

architecture rtl of test is
   constant BYTE_WIDTH : natural := 8;
   subtype  RNG_BYTE1  is natural range BYTE_WIDTH-1 downto 0; -- OK
   type     RNG_BYTE2  is         range BYTE_WIDTH-1 downto 0; -- OK - but how does this get used?
   signal s1, s2, s3 : RNG_BYTE2;
begin  --rtl
        s1 <= 4 + s2;
end architecture rtl;

but not in slice for pre-defined array like std_logic_vector/bit_vector etc as their range is predefined natural type.

Regards,
dhiRAj

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of schav9035@mypacks.net
Sent: Wednesday, April 15, 2015 7:14 PM
To: vhdl-200x@eda.org
Subject: RE: {Spam?} Re: [vhdl-200x] VHDL-2008: Records and aggregates

Not sure if this answers your question, but RNG_BYTE1 (below) can be used in slices.  The declaration of RNG_BYTE2 appears to be legal, but I don't know how it gets used (or is useful), as the declaration of byte2 causes an error when I compile it.

 - Woody
----------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity test is
end test;

architecture rtl of test is
   constant BYTE_WIDTH : natural := 8;
   subtype  RNG_BYTE1  is natural range BYTE_WIDTH-1 downto 0; -- OK
   type     RNG_BYTE2  is         range BYTE_WIDTH-1 downto 0; -- OK - but how does this get used?
   signal byte1 : std_logic_vector(RNG_BYTE1);     -- OK
   signal byte2 : std_logic_vector(RNG_BYTE2);     -- "Type of discrete range is different from the corresponding index."
   signal bytes : std_logic_vector(15 downto 0);

begin  --rtl
   byte1 <= bytes(RNG_BYTE1);
   byte2 <= bytes(RNG_BYTE2);  -- Not sure if this is ok because of error in declaring byte2.
end architecture rtl;


-----Original Message-----
>From: "Lehmann, Patrick" <patrick.lehmann@tu-dresden.de>
>Sent: Apr 15, 2015 4:57 AM
>To: "vhdl-200x@eda.org" <vhdl-200x@eda.org>
>Subject: RE: {Spam?} Re: [vhdl-200x] VHDL-2008: Records and aggregates
>
>Hello,
>
>Sorry I was not aware of that it's possible to use range
>> type myRange is RANGE 7 downto 0;
>without any integer type/subtype or similar.
>
>Any other suggestions to declare a pure range? Or alternatively, any
>suggestions to use integer type/subtype definitions as a range in
>slices and aggregates?
>
>Regards
>    Patrick
>
>


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