On 10/04/15 18:32, Jim Lewis wrote: > Hi, > I just ran into an interesting issue with VHDL-2008 aggregates. In > VHDL-2008, we allowed aggregates to effectively do concatenation when > the target is an array. > > Unfortunately this means you have a to_string function that is > overloaded to handle records, it is now ambiguous since the record > aggregate can also be interpreted as std_logic_vector. > > write (buf, to_string( (UartRxRec.Data, UartRxRec.ErrorMode) )) ; No, this is ambiguous since VHDL 87, as the type of an aggregate is determined by the context. > If you use named aggregates, this is not an impact. However, if you do > not, it may be a significant impact. No, that's not correct. Use of association by name has no impact for determining the type. Tristan. > Hence, now you have to add a type qualifier. This is an unfortunate > side-effect. > write (buf, to_string( UartStimType'(UartRxRec.Data, > UartRxRec.ErrorMode) )) ; > > The original change was targeted at handling situations like: > (CarryOut, Sum_unsigned) <= ('0' & A_unsigned) + B_unsigned ; > > And also handles situations like: > (ExtraBit, Accumulate_ufixed) <= Accumulate_ufixed + A_ufixed ; > > Really wish we had allowed concatenation on the LHS instead. > > We may need to look into how big of an impact this causes. > > Jim > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Apr 10 11:59:13 2015
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